Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
1
M2S56D20TP is a 4-bank x 16777216-word x 4-bit,
M2S56D30TP is a 4-bank x 8388608-word x 8-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30 TP achieves very high
speed data rate up to 133MHz, and are suitable for main memory in computer systems.
- Vdd=Vddq=2.5v0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 1.5/2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- FET switch control(/QFC)
- JEDEC standard
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
FEATURES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU/QFC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66pin TSOP(II)
400mil width
x
875mil length
0.65mm
Lead Pitch
ROW
A0-12
Column
A0-9,11(x4)
A0-9 (x8)
x8
PIN CONFIGURATION
(TOP VIEW)
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
2
CLK,/CLK
: Master Clock
CKE
: Clock Enable
/CS
: Chip Select
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQ0-7
: Data I/O
DQS
: Data Strobe
DM
: Write Mask
/QFC
: FET Switch Control
Vref
: Reference Voltage
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU,/QFC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66pin TSOP(II)
400mil width
x
875mil length
0.65mm
Lead Pitch
ROW
A0-12
Column
A0-9,11(x4)
A0-9 (x8)
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU,/QFC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
x4
A0-12
: Address Input
BA0,1
: Bank Address Input
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
3
Type Designation Code
This rule is applied to only Synchronous DRAM family.
Mitsubishi Main Designation
Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0
75: 133MHz@CL=2.5,100MHz@CL=2.0
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2n 2: x4, 3: x8
DDR Synchronous DRAM
Density 56: 256M bits
Interface V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
M 2 S 56 D 3 0
TP -
BLOCK DIAGRAM
/CS /RAS /CAS /WE
DM
Memory
Array
Bank #0
DQ0 - 7
I/O Buffer
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
A0-12
BA0,1
Clock Buffer
CLK,/CLK
CKE
Control Signal Buffer
/QFC
QFC&QS Buffer
DQS
DLL
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
4
PIN FUNCTION
CLK,/CLK
Input
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4) and A0-9(x8). A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
Input
DQ0-7(x8),
DQ0-3(x4)
Input / Output
DQS
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
SYMBOL
TYPE
DESCRIPTION
/QFC
Output
FET Control: Optional. Output during every Read and Write access. Can
be used to control
isolation switches on modules. Open drain output.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM pins
are input only, the DM loading matches the DQ and DQS loading.
Input / Output
Vref
Input
SSTL_2 reference voltage.
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
5
BASIC FUNCTIONS
The M2S56D20/30TP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
CLK
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-
precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
/CLK
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
6
COMMAND TRUTH TABLE
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/CS
/RAS
/CAS
/WE
BA0,1
A10
/AP
A0-9,
11-12
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with
Auto-Precharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry
& Read with
Auto-Precharge
READA
H
X
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TERM
H
X
L
H
H
L
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
V
X
note
1
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 =
1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-
code to be written to the selected Mode Register.
2
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
7
FUNCTION TRUTH TABLE
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE / PREA
NOP
L
L
L
H
X
REFA
Auto-Refresh
L
L
L
L
Op-Code,
Mode-Add
MRS
Mode Register Set
ROW ACTIVE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
NOP
L
H
L
H
BA, CA, A10
READ / READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ
(Auto-
Precharge
Disabled)
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE
WRITEA
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Notes
2
2
2
4
5
5
3
2
ILLEGAL
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
8
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
WRITE
(Auto-
Precharge
Disabled)
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin Read, Determine Auto-
Precharge
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
PRECHARGE/ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
PRECHARGE/ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Notes
3
3
2
2
2
2
2
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
9
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
PRE -
CHARGING
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
NOP (Idle after tRP)
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW
ACTIVATING
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE RE-
COVERING
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Notes
2
2
2
4
2
2
2
2
2
2
2
2
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
10
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
RE-
FRESHING
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MODE
REGISTER
SETTING
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
Notes
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
11
Current State
CKE
n-1
CKE
n
/CS /RAS /CAS /WE
Add
Action
SELF-
REFRESH
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
POWER
DOWN
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
ALL BANKS
IDLE
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State =Power Down
ANY STATE
other than
listed above
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle
L
L
X
X
X
X
X
Maintain CLK Suspend
FUNCTION TRUTH TABLE for CKE
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be
satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
Notes
3
3
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
12
SIMPLIFIED STATE DIAGRAM
ROW
ACTIVE
IDLE
PRE
CHARGE
POWER
DOWN
READ
READA
WRITE
WRITEA
POWER
ON
ACT
REFA
REFS
REFSX
CKEL
CKEH
MRS
CKEL
CKEH
WRITE
READ
WRITEA
WRITEA
READA
READ
PRE
READA
READA
PRE
PRE
PREA
POWER
APPLIED
MODE
REGISTER
SET
SELF
REFRESH
AUTO
REFRESH
Active
Power
Down
Automatic Sequence
Command Sequence
WRITE
READ
PRE
CHARGE
ALL
MRS
BURST
STOP
TERM
Sep.'99 Preliminary
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ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
13
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when both banks are
in idle state. After tRSC from a MRS command, the DDR SDRAM is
ready for new command.
R: Reserved for Future Use
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Burst
Length
BT= 0
BT= 1
R
2
4
8
R
R
R
R
R
2
4
8
R
R
R
R
0
1
Burst
Type
Sequential
Interleaved
A11 A10 A9
A8
A7
A6
A5
A4
A3 A2
A1
A0
BA1 BA0
0
0
DR
0
LTMODE
BT
BL
0
0
0
/CS
/RAS
/CAS
/WE
A11-A0
/CLK
V
CLK
BA0
BA1
CL
Latency
Mode
/CAS Latency
R
R
2
R
R
1.5
2.5
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
DLL
Reset
NO
YES
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
14
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued when all banks are
in idle state. After tRSC from a EMRS command, the DDR SDRAM is ready
for new command.
/CS
/RAS
/CAS
/WE
A11-A0
/CLK
V
CLK
BA0
BA1
0
1
DLL
Disable
DLL enable
DLL disable
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1 BA0
0
0
0
0
DD
1
0
0
DS
QFC
0
0
0
0
0
1
Drive
Strength
Normal
Weak
0
1
QFC
Disable
Enable
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
15
/CAS Latency
Burst Length
CL= 2
BL= 4
Burst Length
A2
A1
A0
Initial Address BL
Sequential
Interleaved
Column Addressing
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
-
0
0
-
0
1
-
1
0
-
1
1
-
-
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
7
0
1
2
0
1
2
3
1
2
3
0
2
3
0
1
3
0
0
1
7
6
5
4
0
1
2
3
1
0
3
2
2
3
0
1
3
2
0
1
-
-
1
1
2
1
0
3
4
5
6
3
2
1
0
1
0
1
0
8
4
2
Command
Address
DQ
Y
Y
Read
Write
DQS
Q0 Q1 Q2 Q3
D0 D1 D2 D3
/CLK
CLK
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
16
ABSOLUTE MAXIMUM RATINGS
DC OPERATING CONDITIONS
(Ta=0 ~ 70C, unless otherwise noted)
CAPACITANCE
(Ta=0 ~ 70C, Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 3.7
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ VddQ+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25 C
1000
mW
Topr
Operating Temperature
0 ~ 70
C
Tstg
Storage Temperature
-65 ~ 150
C
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
Vdd
Supply Voltage
2.3
2.5
2.7
V
VddQ
Supply Voltage for Output
2.3
2.5
2.7
V
VIH(DC)
High-Level Input Voltage
Vref + 0.18
VddQ+0.3
V
VIL(DC)
Low-Level Input Voltage
-0.3
Vref - 0.18
V
11
pF
3.5
2.5
CO(QF) Output Capacitance, /QFC
11
pF
5.5
4.0
11
pF
3.5
2.5
11
pF
3.5
2.5
11
pF
3.5
2.5
I/O Capacitance, I/O, DQS, DM pin
CI/O
Input Capacitance, CLK pin
CI(K)
Input Capacitance, control pin
CI(C)
Input Capacitance, address pin
CI(A)
VI=1.25v
f=100MHz
VI=25mVrms
Notes
Unit
Max.
Min.
Limits
Test Condition
Parameter
Symbol
Vref
Input Reference Voltage
1.15
1.35
V
1.25
VIN(DC)
Input Voltage Level, CLK and /CLK
-0.3
VddQ + 0.3
V
VID(DC) Input Differential Voltage, CLK and /CLK
0.36
VddQ + 0.6
V
VTT
I/O Termination Voltage
Vref - 0.04
V
Vref + 0.04
Notes
6
5
7
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
17
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70C, Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, unless otherwise noted)
mA
9
2
160
120
140
50
15
12
12
90
2
150
mA
mA
30
110
-75
SELF REFRESH CURRENT: CKE
0.2V
AUTO REFRESH CURRENT:
t
RC =
t
RFC (MIN)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; CL = 2.5;
t
CK =
t
CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One
bank active; Address and control inputs changing once per clock
cycle; CL = 2.5;
t
CK =
t
CK MIN; I
OUT
= 0 mA
ACTIVE STANDBY CURRENT: /CS > V
IH
(MIN); CKE > V
IH
(MIN);
One bank; Active-Precharge;
t
RC =
t
RAS MAX;
t
CK =
t
CK MIN;
DQ,DM and DQS inputs changing twice per clock cycle; address
and other control inputs changing once per clock cycle
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
power-down mode; CKE
V
IL
(MAX);
t
CK =
t
CK MIN
IDLE STANDBY CURRENT: /CS > V
IH
(MIN); All banks idle;
CKE > V
IH
(MIN);
t
CK =
t
CK MIN; Address and other control inputs
changing once per clock cycle
IDD2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks
idle; power-down mode; CKE
V
IL
(MAX);
t
CK =
t
CK MIN
mA
OPERATING CURRENT: One Bank; Active-Read-Precharge;
Burst = 2;
t
RC =
t
RC MIN; CL = 2.5;
t
CK =
t
CK MIN; I
OUT
= 0
mA;Address and control inputs changing once per clock cycle
OPERATING CURRENT: One Bank; Active-Precharge;
t
RC =
t
RC MIN;
t
CK =
t
CK MIN; DQ, DM and DQS inputs
changing twice per clock cycle; address and control inputs changing
once per clock cycle
Parameter/Test Conditions
120
50
IDD4R
IDD3N
mA
mA
mA
mA
mA
mA
100
15
30
100
80
IDD6
IDD5
IDD4W
IDD3P
IDD2N
IDD1
IDD0
Notes
Unit
-10
Limits(max)
Symbol
Symbol
Parameter/Test Conditions
Limits
Min.
Max.
Unit
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
High-Level Input Voltage (AC)
Low-Level Input Voltage (AC)
Input Differential Voltage, CLK and /CLK
Input Crossing Point Voltage, CLK and /CLK
Vref + 0.35
Vref - 0.35
V
V
V
V
0.7
0.5*V
DD
Q-0.2
V
DD
Q + 0.6
IOZ
I
I
Off-state Output Current /Q floating Vo=0~V
DD
Q
Input Current / VIN=0 ~ VddQ
A
A
-5
-5
5
5
0.5*V
DD
Q+0.2
Notes
7
8
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
18
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, unless otherwise noted)
ns
15
12
15
12
CL=1.5
CL=2
CLK cycle time
tCK
CL=2.5
ns
15
10
15
10
16
15
14
14
AC Characteristics
-10
-75
2
1.25
2
1.25
4
4
1.1
0.9
1.1
0.9
0.6
0.4
0.6
0.4
1.1
0.9
1.1
0.9
0.6
0.4
0.6
0.4
1.2
1.1
1.2
1.1
0.25
0.25
0.6
0.4
0.6
0.4
0
0
15
15
0.2
0.2
0.2
0.2
0.35
0.35
0.35
0.35
1.25
0.75
1.25
0.75
0.35
0.35
+0.6
-0.6
+0.5
-0.5
+0.8
-0.8
+0.75
-0.75
+0.8
-0.8
+0.75
-0.75
2
1.75
ns
ns
tCK
tCK
tCK
tCK
ns
ns
tCK
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
0.6
0.5
0.6
0.5
15
8
15
7.5
tCK
0.55
0.45
0.55
0.45
tCK
0.45
0.55
0.45
+0.8
-0.8
+0.75
-0.75
+0.8
-0.8
+0.75
-0.75
Max.
Min.
Max.
Min.
Parameter
0.55
tQOH
tQCK
/QFC output hold time for writes
/QFC output access time from CLK//CLK, for write
/QFC postamble during reads
tQPST
/QFC preamble during reads
tQPRE
Read preamble
tRPRE
Read postamble
tRPST
tWPRE
Write preamble
tWPST
Write postamble
tWPRES Write preamble setup time
Input Hold time (address and control)
tIH
tIS
Input Setup time (address and control)
tMRD
Mode Register Set command cycle time
tDSH
DQS falling edge hold time from CLK
tDSS
DQS falling edge to CLK setup time
tDQSL
DQS input Low level width
tDQSH
DQS input High level width
tDQSS
Write command to first DQS latching transition
tDV
DQ and DQS data Valid window
tDQSQ
DQ Valid data delay time from DQS
Data-out-low impedance time from CLK//CLK
tLZ
tHZ
Data-out-high impedance time from CLK//CLK
tDIPW
DQ and DM input pulse width (for each input)
Input Hold time(DQ,DM)
Input Setup time (DQ,DM)
tDS
tDH
tCL
CLK Low level width
tCH
CLK High level width
ns
DQ Output Valid data delay time from CLK//CLK
tDQSCK
DQ Output Valid data delay time from CLK//CLK
ns
tAC
Notes
Unit
Symbol
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
19
18
17
7.8
7.8
1
1
1
1
200
200
80
75
1
1
15
15
15
15
20
20
20
20
80
75
70
65
120,000
50
120,000
45
us
tCK
tCK
tCK
ns
tCK
ns
ns
ns
ns
ns
Average Periodic Refresh interval
tREFI
Exit Power down to -Read command
tXPRD
Exit Power down to command
tXPNR
tXSRD
Exit Self Ref. to -Read command
tXSNR
Exit Self Ref. to non-Read command
tWTR
Internal Write to Read Command Delay
ns
35
35
Auto Precharge write recovery + precharge time
tDAL
-10
-75
AC Characteristics
Max.
Min.
Max.
Min.
Parameter
tWR
Write Recovery time
tRRD
Act to Act Delay time
Row Precharge time
Row to Column Delay
tRP
tRCD
tRFC
Auto Ref. to Active/Auto Ref. command period
ns
Row Cycle time(operation)
tRC
Row Active time
ns
tRAS
Notes
Unit
Symbol
Output Load Condition
DQ
Output Timing
Measurement
Reference Point
V
REF
V
REF
DQS
V
OUT
V
REF
30pF
50
V
TT
=V
REF
Zo=50
V
TT
=V
REF
50
25
10cm
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70C, Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
20
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified
AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between
VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch
as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back
above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed +/-2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of
the same.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = +2.5V 0.2V, Vdd = +2.5V 0.2V , f = 100 MHz, Ta = 25C, VOUT(DC) =
VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in loading (to facilitate trace matching at the board level).
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross;
the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE =<
0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When
no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous
write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
Sep.'99 Preliminary
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
21
/CLK
DQS
tIS
tIH
VREF
CLK
Valid Data
/QFC
Read Operation
tAC
tDQSCK
tCL
tCH
tCK
tDQSQ
tDV
tRPRE
tRPST
DQS
/QFC
/CLK
CLK
tDQSS
tDS
tDH
tDQSL
tDQSH
tWPRE
Write Operation / tDQSS=max.
tDSS
tWPRES
tWPST
tQCK
tQOH(min)
tQPRE
tQPST
DQS
/QFC
/CLK
CLK
tDQSS
tDS
tDH
tDQSL
tDQSH
tWPRE
Write Operation / tDQSS=min.
tDSH
tWPRES
tWPST
tQCK
tQOH(max)
DQ
DQ
DQ
Cmd &
Add.
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DDR SDRAM (Rev.0.0)
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256M Double Data Rate Synchronous DRAM
22
A precharge command can be issued at BL/2 from a read command without data loss.
Precharge all
Bank Activation and Precharge All (BL=8, CL=2)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
tRAS
tRP
tRCmin
2 ACT command / tRCmin
DQS
Qa0
BL/2
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command
with the bank addresses (BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands
are allowed within tRC,although the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same
time. After tRP from the precharge, an ACT command to the same bank can be issued.
Qa1
Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
/CLK
CLK
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256M Double Data Rate Synchronous DRAM
23
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
READ
Y
0
10
ACT
Xb
Xb
10
PRE
0
00
tRCD
/CAS latency
Burst Length
DQS
Qa0
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the
Burst Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8), and the address
sequence of burst data is defined by the Burst Type. A READ command may be applied to any active
bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the
multiple banks. When A10 is high at a READ command, the auto-precharge(READA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at BL/2 after READA. The next ACT
command can be issued after (BL/2+tRP) from the previous READA.
CLK
Qa1 Qa2 Qa3
Qa4 Qa5 Qa6 Qa7 Qb0 Qb1
Qb2 Qb3 Qb4 Qb5 Qb7 Qb8
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
24
READ with Auto-Precharge (BL=8, CL=2)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
1
00
ACT
Xb
Xb
00
Internal precharge start
tRCD
tRP
BL/2 + tRP
BL/2
DQS
/CLK
CLK
READ Auto-Precharge Timing (BL=8)
Command
ACT
READ
Internal Precharge Start Timing
DQ
DQ
CL=2.5
CL=1.5
BL/2
Qa0
DQ
CL=2
Qa0
/CLK
CLK
Qa0 Qa1 Qa2 Qa3
Qa4 Qa5 Qa6 Qa7
Qa0 Qa1 Qa2
Qa3 Qa4 Qa5 Qa6 Qa7
Qa1 Qa2 Qa3 Qa4
Qa5 Qa6 Qa7
Qa1 Qa2 Qa3 Qa4
Qa5 Qa6 Qa7
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
25
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM, when the Burst
Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8), and the address sequence of
burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the
row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks.
From the last data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at
a WRITE command, the auto-precharge(WRITEA) is performed. Any
command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is complete.
The next ACT command can be issued after tDAL from the last input data cycle.
Multi Bank Interleaving WRITE (BL=8)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
00
WRITE
00
WRITE
0
0
10
ACT
Xb
10
0
10
tRCD
tRCD
PRE
Xa
0
00
PRE
DQS
WRITE with Auto-Precharge (BL=8)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
00
WRITE
1
00
ACT
Xb
00
tRCD
Da0
DQS
/CLK
CLK
/CLK
CLK
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
Db1
Db2
Db3
tDAL
Db4
Db5
Db6
Db7
Xa
Y
Xb
Xa
Ya
Yb
Xb
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
26
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As
a result, READ to PRE interval determines valid data length to be output. The figure below shows
examples of BL=8.
Read Interrupted by Precharge (BL=8)
CL=2.5
Command
DQS
Command
DQ
Command
DQ
Q0
Q1
Q2
Q3
Q0
Q1
Read Interrupted by Read (BL=8, CL=2)
Command
A0-9,11
A10
BA0,1
DQ
Yi
READ READ
READ
READ
Yj
Yk
Yl
0
0
0
0
00
10
00
01
DQS
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
/CLK
CLK
/CLK
CLK
DQ
Q0
Q1
Q2
Q3
Q4
Q5
PRE
READ
READ
PRE
READ PRE
DQS
DQS
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
27
Read Interrupted by Precharge (BL=8)
CL=2.0
/CLK
CLK
Command
DQS
Command
DQ
Command
DQ
Q0
Q1
Q2
Q3
Q0
Q1
DQ
Q0
Q1
Q2
Q3
Q4
Q5
PRE
READ
READ
PRE
READ PRE
DQS
DQS
Command
DQS
Command
DQ
Command
DQ
Q0
Q1
Q2
Q3
Q0
Q1
DQ
Q0
Q1
Q2
Q3
Q4
Q5
PRE
READ
READ
PRE
READ PRE
DQS
DQS
CL=1.5
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
28
[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval
is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to TERM interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by TERM (BL=8)
CL=2.5
Command
DQS
Command
DQ
Command
DQ
Q0
Q1
Q2
Q3
Q0
Q1
/CLK
CLK
DQ
Q0
Q1
Q2
Q3
Q4
Q5
TERM
READ
READ
TERM
READ
TERM
DQS
DQS
CL=2.0
Command
DQS
Command
DQ
Command
DQ
Q0
Q1
Q2
Q3
Q0
Q1
DQ
Q0
Q1
Q2
Q3
Q4
Q5
TERM
READ
READ
TERM
READ
TERM
DQS
DQS
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
29
[Read Interrupted by Write with TERM]
Read Interrupted by TERM (BL=8)
CL=2.5
Command
DQ
Q0
Q1
Q2
Q3
/CLK
CLK
READ
TERM
DQS
WRITE
D0
D1
D2
D3
D4
D5
CL=2.0
Command
DQ
Q0
Q1
Q2
Q3
READ
TERM
DQS
WRITE
D0
D1
D2
D3
D4
D5
D6
D7
CL=1.5
Command
DQ
Q0
Q1
Q2
Q3
READ
TERM
DQS
WRITE
D0
D1
D2
D3
D4
D5
D6
D7
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
30
Write Interrupted by Write (BL=8)
Command
A0-9,11
A10
BA0,1
WRITE
Yi
0
00
WRITE
Yk
0
10
WRITE
Yj
0
00
WRITE
Yl
0
00
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data on DQ
at the interrupting READ cycle is "don't care". tWTR is referenced from the first positive edge after the
last data input.
DQ
Dai1
Daj1
Daj3
Dak1
Dak3
Dak5
Dal1
DQS
Dal2 Dal3
Dal5
Dal6 Dal7
Dal4
Dal0
Dak4
Dak2
Dak0
Dai0
Daj0
Daj2
/CLK
CLK
Write Interrupted by Read (BL=8, CL=2.5)
Command
A0-9,11-12
A10
BA0,1
DQ
WRITE
Yi
0
00
READ
Yj
0
00
Dai0
Dai1
Qaj0 Qaj1 Qaj2 Qaj3
QS
Qaj4 Qaj5 Qaj6 Qaj7
DM
tWTR
/CLK
CLK
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
31
[Write interrupted by Precharge]
Write Interrupted by Precharge (BL=8, CL=2.5)
Command
A0-9,11-12
A10
BA0,1
DQ
WRITE
Yi
0
00
PRE
00
Dai0
Dai1
QS
Burst write operation can be interrupted by precharge of the same or all bank. Random column access is
allowed. tWR is referenced from the first positive CLK edge after the last data input.
DM
tWR
/CLK
CLK
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
32
[Initialize and Mode Register sets]
Command
/CLK
CLK
EMRS
PRE
NOP
MRS
PRE
AR
AR
MRS
ACT
Code
Code
Xa
Code
Xa
1 0
Xa
A0-9,11,12
A10
Code
1
BA0,1
DQS
DQ
1
0 0
0 0
Code
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command.
The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbits memory
cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all
banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command
must not be supplied to the device before tRFC from the REFA command.
Auto-Refresh
/RAS
CKE
/CS
/CAS
/WE
A0-12
BA0,1
NOP or DESELECT
tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
/CLK
CLK
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
33
[SELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once
the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE
is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that
power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK
inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD.
Self-Refresh
/RAS
CKE
/CS
/CAS
/WE
A0-12
BA0,1
tXSNR
Self Refresh Exit
/CLK
CLK
X
Y
X
Y
tXSRD
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
34
[Asynchronous SELF REFRESH]
Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command
(/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept
low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs
including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved.
To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then
asserting CKE for longer than tXSNR/tXSRD.
Asynchronous Self-Refresh
/RAS
CKE
/CS
/CAS
/WE
A0-12
BA0,1
tXSNR
Self Refresh Exit
max 2 tCLK
/CLK
CLK
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256M Double Data Rate Synchronous DRAM
35
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh
mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT
required in the condition of the stable CLK operation during the power down mode.
/CLK
CLK
Power Down by CKE
Command
PRE
CKE
Command
ACT
CKE
Standby Power Down
Active Power Down
NOP
NOP
DM Function(BL=8,CL=2)
Command
DQS
DQ
DM
Write
READ
D0 D1
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM to
write mask latency is 0.
D3 D4
D5 D6
D7
masked by DM=H
Don't Care
Q2
Q3
Q4
Q5
/CLK
CLK
Q0
Q1
Q6
Valid
NOP
NOP
Valid
tXPNR/
tXPRD
Sep.'99 Preliminary
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DDR SDRAM (Rev.0.0)
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
36
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the possibility
that trouble may occur with them. Trouble with semiconductors consideration to
safety when making your circuit designs,with appropriate measures such as (i)
placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii)
prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection
of the Mitsubishi semiconductor product best suited to the customer's
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any other rights,belonging to Mitsubishi Electric Corporation or a third party.
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